Design Guidelines of a VHDL-based Simulation Tool for the Validation of Fault Tolerance

This paper addresses the problem of the validation of fault tolerance mechanisms during the design of fault-tolerant computing systems. It presents an integrated environment for applying fault injection into simulation models encompassing various levels of abstraction. First, the expected benefits of the approach are clearly identified in relation to other fault injection methods available. Then the use of VHDL as the simulation language is motivated. Four techniques for injecting faults into VHDL models are described: two techniques require the modification of the VHDL model, while the other two rely on the commands available in the simulator to inject faults during the execution of the simulation; their respective merits are analysed and compared. A tool implementing all the considered techniques is presented. An object-oriented paradigm is proposed to be used to handle the fault injection techniques. A functional overview of the tool is given that describes the various functional phases: setup, simulation, and data processing. Finally, some relevant implementation issues are presented.